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1 ? X9221A 64 taps, 2-wire serial bus dual digitally contro lled potentiometer (xdcp?) features ? two xdcps in one package ? 2-wire serial interface ? register oriented format, 8 registers total ?directly write wiper position ?read wiper position ?store as many as four positions per pot ? instruction format ?quick transfer of register contents to resistor array ? direct write cell ?endurance?100,000 writes per bit per register ? resistor array values ?2k , 10k , 50k ? resolution: 64 taps each pot ? 20 ld plastic dip and 20 ld soic packages ? pb-free plus anneal available (rohs compliant) description the X9221A integrates two digitally controlled potenti- ometers (xdcp) on a monolithic cmos integrated microcircuit. the digitally controlled potentiometer is implemented using 63 resistive elements in a series array. between each element are tap points connected to the wiper terminal through switches. the position of the wiper on the array is controlled by the user through the 2-wire bus interface. each potentiometer has associated with it a volatile wiper counter register (wcr) and 2 non- volatile data registers (dr0 :dr1) that can be directly written to and read by the user. the contents of the wcr controls the pos ition of the wiper on the resistor array through the switches. power up recalls the con- tents of dr0 to the wcr. the xdcp can be used as a three-terminal potentiom- eter or as a two-terminal variable resistor in a wide variety of applications in cluding control, parameter adjustments, and signal processing. block diagram r1 r0 r3 r2 v h0 /r h0 v l0 /r l0 v w0 /r w0 wiper counter register (wcr) register array pot 1 wiper counter register (wcr) r1 r0 r3 r2 8 data scl sda a0 a1 a2 a3 interface and control circuitry v cc v ss pot 0 v h1 /r h1 v l1 /r l1 v w1 /r w1 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. xdcp is a trademark of intersil americas inc. copyri ght intersil americas inc. 2005-2006. all rights reserved all other trademarks mentioned are the property of their respective owners. data sheet fn8163.2 august 30, 2006
ordering information part number part marking v cc limits (v) r total (k) temp range (c) package pkg. dwg. # X9221Ays X9221Ays 5 10% 2 0 to +70 20 ld soic (300mil) mdp0027 X9221Aysz (note) X9221Ays z 0 to +70 20 ld soic (300mil) (pb-free) mdp0027 X9221Aysi* X9221Aysi -40 to +85 20 ld soic (300mil) mdp0027 X9221Aysiz* (note) X9221Aysi z -40 to +85 20 ld soic (300mil) (pb-free) mdp0027 X9221Aws* X9221Aws 10 0 to +70 20 ld soic (300mil) mdp0027 X9221Awsz* (note) X9221Aws z 0 to +70 20 ld soic (300mil) (pb-free) mdp0027 X9221Awsi* X9221Awsi -40 to +85 20 ld soic (300mil) mdp0027 X9221Awsiz* (note) X9221Awsi z -40 to +85 20 ld soic (300mil) (pb-free) mdp0027 X9221Aup X9221Aup 50 0 to +70 20 ld pdip mdp0031 X9221Aupz (note) X9221Aupz 0 to +70 20 ld pdip (pb-free) mdp0031 X9221Aupi X9221Aupi -40 to +85 20 ld pdip mdp0031 X9221Aupiz (note) X9221Aupiz -40 to +85 20 ld pdip (pb-free) mdp0031 X9221Ausi* X9221Ausi -40 to +85 20 ld soic (300mil) mdp0027 X9221Ausiz* (note) X9221Ausi z -40 to +85 20 ld soic (300mil) (pb-free) mdp0027 *add "t1" suffix for tape and reel. note: intersil pb-free plus anneal products empl oy special pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are rohs compli ant and compatible with both snpb and pb-free soldering operation s. intersil pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements o f ipc/jedec j std-020. v w0 /r w0 v l0 /r l0 v h0 /r l0 a0 a2 v w1 /r w1 v l1 /r l1 v h1 /r h1 sda v ss 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 v cc res res res a1 a3 scl res res res dip/soic X9221A 2 fn8163.2 august 30, 2006 pin descriptions host interface pins serial clock (scl) the scl input is used to cloc k data into and out of the X9221A. serial data (sda) sda is a bidirectional pin used to transfer data into and out of the device. it is an open drain output and may be wire-ored with any number of open drain or open collector outputs. an open drain output requires the use of a pull-up resistor. for selecting typical val- ues, refer to the guidelines for calculating typical val- ues on the bus pull-up resistors graph. address the address inputs are used to set the least signifi- cant 4 bits of the 8-bit slave address. a match in the slave address serial data stream must be made with the address input in order to initiate communication with the X9221A potentiometer pins v h /r h (v h0 /r h0 -v h1 /r h1 ), v l /r l (v l0 /r l0 -v l1 /r l1 ) the v h /r h and v l /r l inputs are equivalent to the ter- minal connections on either end of a mechanical potentiometer. v w /r w (v w0 /r w0 -v w1 /r w1 ) the wiper outputs are equivale nt to the wiper output of a mechanical potentiometer. pin configuration X9221A
1 0 0 a3 a2 a1 a0 device type identifier device address 1 3 fn8163.2 august 30, 2006 pin names principles of operation the X9221A is a highly integrated microcircuit incor- porating two resistor arrays, their associated registers and counters and the serial interface logic providing direct communication between the host and the xdcp potentiometers. serial interface the X9221A supports a bidirectional bus oriented pro- tocol. the protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. the device controlling the transfer is a master and the device being controlled is the slave. the master will always initia te data transfers and pro- vide the clock for both transmit and receive operations. therefore, the X9221A will be considered a slave device in all applications. clock and data conventions data states on the sda lin e can change only during scl low periods (t low ). sda state changes during scl high are reserved for indicating start and stop conditions. start condition all commands to the X9221A are preceded by the start condition, which is a high to low transition of sda while scl is high (t high ). the X9221A continu- ously monitors the sda and scl lines for the start condition, and will not resp ond to any command until this condition is met. stop condition all communications must be terminated by a stop con- dition, which is a low to high transition of sda while scl is high. acknowledge acknowledge is a software convention used to provide a positive handshake between the master and slave devices on the bus to indicate the successful receipt of data. the transmitting device, either the master or the slave, will release the sda bu s after transmitting eight bits. the master generates a ninth clock cycle and during this period the receiver pulls the sda line low to acknowledge that it successfully received the eight bits of data. see figure 7. the X9221A will respond wit h an acknowledge after recognition of a start cond ition and its slave address and once again after successful receipt of the com- mand byte. if the command is followed by a data byte the X9221A will respond wit h a final acknowledge. array description the X9221A is comprised of two resistor arrays. each array contains 63 discrete resistive segments that are connected in series. the physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer (v h /r h and v l /r l inputs). at both ends of each array and between each resistor segment is a fet switch connected to the wiper (v w /r w ) output. within each individual array only one switch may be turned on at a time. these switches are controlled by the wiper counter register (wcr). the six least significant bits of the wcr are decoded to select, and enable, one of sixty-four switches. the wcr may be written direct ly, or it can be changed by transferring the contents of one of four associated data registers into the wcr. these data registers and the wcr can be read and written by the host system. device addressing following a start condition the master must output the address of the slave it is accessing. the most signifi- cant four bits of the slave address are the device type identifier (refer to figure 1 below). for the X9221A this is fixed as 0101[b]. figure 1. slave address symbol description scl serial clock sda serial data a0?a3 address v h0 /r h0 -v h1 /r h1 , v l0 /r h0 -v l1 /r l0 potentiometers (terminal equivalent) v w0 /r w0 -v w1 /r w1 potentiometers (wiper equivalent) res reserved (do not connect) X9221A
nonvolatile write command completed enter ack polling issue start issue slave address ack returned? further operation? issue instruction proceed issue stop no yes yes proceed issue stop no 4 fn8163.2 august 30, 2006 the next four bits of the sl ave address are the device address. the physical device address is defined by the state of the a0-a3 inputs. the X9221A compares the serial data stream with the address input state; a successful compare of all four address bits is required for the X9221A to respond with an acknowledge. acknowledge polling the disabling of the inputs, during the internal nonvol- atile write operation, can be used to take advantage of the typical 5ms eeprom writ e cycle time. once the stop condition is issued to indicate the end of the non- volatile write command the X9221A initiates the inter- nal write cycle. ack polling can be initiated immediately. this involves issuing the start condition followed by the device slave address. if the X9221A is still busy with the write operation no ack will be returned. if the X9221A has completed the write oper- ation an ack will be returned and the master can then proceed with the next operation. flow 1. ack polling sequence instruction structure the next byte sent to the X9221A contains the instruc- tion and register pointer information. the four most significant bits are the inst ruction. the next four bits point to one of two pots and when applicable they point to one of four associated registers. the format is shown below in figure 2. figure 2. instruction byte format t i1 i2 i3 i0 0 p0 r1 r0 potentiometer select register select instructions the four high order bits define the instruction. the sixth bit (p0) selects which one of the two potentiome- ters is to be affected by th e instruction. the last two bits (r1 and r0) select one of the four registers that is to be acted upon when a register oriented instruction is issued. four of the nine instructions end with the transmission of the instruction byte. th e basic sequence is illus- trated in figure 3. these two-byte instructions exchange data between the wcr and one of the data registers. a transfer from a data register to a wcr is essentially a write to a stat ic ram. the response of the wiper to this action will be delayed t stpwv . a transfer from wcr?s current wiper position to a data register is a write to nonv olatile memory and takes a minimum of t wr to complete. the transfer can occur between either potentiometer and their associated registers or it may occur between both of the potenti- ometers and one of their associated registers. four instructions require a three-byte sequence to complete. these instructions transfer data between the host and the X9221A; either between the host and one of the data registers or directly between the host and the wcr. these instru ctions are: read wcr, read the current wiper position of the selected pot; write wcr, change curren t wiper position of the selected pot; read data regi ster, read the contents of the selected nonvolatile regi ster; write data register, write a new value to the selected data register. the sequence of operations is shown in figure 4. the increment/decrement command is different from the other commands. once the command is issued and the X9221A has responded with an acknowledge, the master can clock the selected wiper up and/or down in one segment steps; thereby, providing a fine X9221A
s t a r t 0101a3a2a1a0 a i3 i2 i1 i0 0 p0 r1 r0 scl sda s t o p c k a c k s t a r t 0 1 0 1 a3 a2 a1 a0 a i3 i2 i1 i0 0 p0 r1 r0 scl sda s t o p 0 0 d5 d4 d3 d2 d1 d0 c k a c k a c k 5 fn8163.2 august 30, 2006 tuning capability to the host . for each scl clock pulse (t high ) while sda is high, the selected wiper will move one resistor se gment towards the v h /r h termi- nal. similarly, for each sc l clock pulse while sda is low, the selected wiper will move one resistor seg- ment towards the v l /r l terminal. a detailed illustra- tion of the sequence and timing for this operation are shown in figures 5 and 6 respectively. figure 3. two-byte command sequence figure 4. three-byte command sequence figure 5. increment/decrement command sequined e s t a r t 0 1 0 1 a3 a2 a1 a0 i3 i2 i1 i0 0 p0 r1 r0 scl sda s t o p x x i n c 1 i n c 2 i n c n d e c 1 d e c n a c k a c k X9221A
scl sda v w /r w inc/dec cmd issued voltage out t clwv 6 fn8163.2 august 30, 2006 figure 6. increment/de crement timing limits table 1. instruction set note: (7) n/a = not applicable or don?t care; that is, a data regist er is not involved in the operation and need not be addressed (typ ical) instruction instruction format operation i 3 i 2 i 1 i 0 0p 0 r 1 r 0 read wcr 1 0 0 1 0 1/0 n/a (7) n/a read the contents of the wiper counter register pointed to by p 0 write wcr 1 0 1 0 0 1/0 n/a n/a write new value to the wiper counter register pointed to by p 0 read data register 1 0 1 1 0 1/0 1/0 1/0 read the contents of the register pointed to by p 0 and r 1 ?r 0 write data register 1 1 0 0 0 1/0 1/0 1/0 write new value to the register pointed to by p 0 and r 1 ?r 0 xfr data register to wcr 1 1 0 1 0 1/0 1/0 1/0 transfer the contents of the register pointed to by p 0 and r 1 ?r 0 to its associated wcr xfr wcr to data register 1 1 1 0 0 1/0 1/0 1/0 transfer the contents of the wcr pointed to by p 0 to the register pointed to by r 1 ?r 0 global xfr data register to wcr 0 0 0 1 n/a n/a 1/0 1/0 transfer the contents of the data registers pointed to by r 1 ?r 0 of both pots to their respective wcr global xfr wcr to data register 1 0 0 0 n/a n/a 1/0 1/0 transfer the contents of all wcrs to their respective data registers pointed to by r 1 ?r 0 of both pots increment/decrement wiper 0 0 1 0 0 1/0 n/a n/a enable increment/decrement of the wcr point- ed to by p 0 X9221A
scl from data output 1 89 start acknowledge master from transmitter data output from receiver 7 fn8163.2 august 30, 2006 figure 7. acknowledge response from receiver detailed operation both xdcp potentiometers share the serial interface and share a common architecture. each potentiometer is comprised of a resistor array, a wiper counter regis- ter and four data registers. a detailed discussion of the register organization and array operation follows. wiper counter register the X9221A contains two wiper counter registers (wcr), one for each xdcp potentiometer. the wcr can be envisioned as a 6-bit parallel and serial load counter with its outputs decoded to select one of sixty- four switches along its resist or array. the contents of the wcr can be altered in fo ur ways: it may be written directly by the host via the write wcr instruction (serial load); it may be writt en indirectly by transferring the contents of one of four associated data registers via the xfr data register inst ruction (parallel load); it can be modified one step at a time by the increment/ decrement instruction; finally, it is loaded with the con- tents of its data register zero (r0) upon power-up. the wcr is a volatile register; that is, its contents are lost when the X9221A is powered-down. although the register is automatically loaded with the value in r0 upon power-up, it should be noted this may be differ- ent from the value present at power-down. data registers each potentiometer has four nonvolatile data regis- ters. these can be read or written directly by the host and data can be transferred between any of the four data registers and the wcr. it should be noted all operations changing data in one of these registers is a nonvolatile operation and will take a maximum of 10ms. if the application does not require storage of multiple settings for the potentiometer, these registers can be used as regular memory locations that could possibly store system parameters or user preference data. X9221A
serial data path from interface circuitry register 0 register 1 register 2 register 3 serial bus input parallel bus input wiper counter register inc/dec logic up/dn clk modified scl up/dn v h /r h if wcr = 00[h] then v w /r w = v l /r l if wcr = 3f[h] then v w /r w = v h /r h 8 6 c d e o u n t e r e c o d v l /r l v w /r w 8 fn8163.2 august 30, 2006 figure 8. detailed potentiometer block diagram X9221A
recommended operating conditions temp min. max. commercial 0 q c+70 q c industrial -40 q c+85 q c supply voltage limits X9221A 5v 10% 9 fn8163.2 august 30, 2006 absolute maximum ratings temperature under bias ................... -65c to +135c storage temperature ........................ -65c to +150c voltage on sck, scl or any address input with respect to v ss ...................... -1v to +7v voltage on any v h /r h , v w /r w or v l /r l referenced to v ss ................................. +6v / -4.3v ' v = |v h /r h ?v l /r l |........................................... 10.3v lead temperature (soldering, 10s) ................. +300c i w (10s) ..............................................................6ma comment stresses above those liste d under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only; functional operation of the device (at these or any ot her conditions above those indicated in the operational sections of this specifica- tion) is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. analog characteristics (over recommended operating condi tions unless otherwise stated.) symbol parameter limits test conditions min. typ. max. unit r total end to end resistance -20 +20 % power rating 50 mw +25c, each pot i w wiper current -3 +3 ma r w wiper resistance 40 130 : wiper current = 1ma v term voltage on any v h /r h , v w /r w or v l /r l pin -3.0 +5 v noise d 120 dbv ref: 1v resolution 1.6 % see note 5 absolute linearity (1) -1 +1 mi (3) v w(n)(actual - v w(n)(expected) relative linearity (2) -0.2 +0.2 mi (3) v w(n + 1) - [v w(n) + mi ] temperature coefficient 300 ppm/c see note 5 radiometric temperature coef ficient 20 ppm/c see note 5 c h /c l /c w potentiometer capacitances 10/10/25 pf see circuit #3 X9221A
10 fn8163.2 august 30, 2006 d.c. operating characteristics (over recommended operating condi tions unless otherwise stated.) notes: (1) absolute linearity is utilized to determi ne actual wiper voltage versus expected vo ltage as determined by wiper position whe n used as a potentiometer. (2) relative linearity is utilized to determi ne the actual change in voltage between two successive tap positions when used as a potenti- ometer. it is a measure of the error in step size. (3) mi = rtot/63 or (v h /r h ?v l /r l )/63, single pot endurance and data retention capacitance power-up timing notes: (5) this parameter is periodically sampled and not 100% tested. (6) t pur and t puw are the delays required from the time v cc is stable until the specified operation can be initiated. these parameters are periodically sampled and not 100% tested. power up requirements (power up sequencing can affect correct recall of the wiper registers) the preferred power-on sequence is as follows: first v cc , then the potentiometer pi ns. it is suggested that v cc reach 90% of its final value before power is applied to the potentiometer pins. the v cc ramp rate specification should be met, and any glitches or slope changes in the v cc line should be held to <1 00mv if possible. also, v cc should not reverse polarity by more than 0.5v. symbol parameter limits test conditions min. typ. max. unit l cc supply current (active) 3 ma f scl = 100khz, sda = open, other inputs = v ss i sb v cc current (standby) 200 500 a scl = sda = v cc , addr. = v ss i li input leakage current 10 a v in = v ss to v cc i lo output leakage current 10 a v out = v ss to v cc v ih input high voltage 2 v cc + 1 v v il input low voltage -1 0.8 v v ol output low voltage 0.4 v i ol = 3ma parameter min. unit minimum endurance 100,000 data changes per bit per register data retention 100 years symbol parameter max. unit test conditions c i/o (5) input/output capacitance (sda) 8 pf v i/o = 0v c in (5) input capacitance (a0, a1, a2, a3 and scl) 6 pf v in = 0v symbol parameter min. max. unit t pur (6) power-up to initiation of read operation 1 ms t puw (6) power-up to initiation of write operation 5 ms t r v cc v cc power-up ramp rate 0.2 50 v/ms X9221A
waveform inputs outputs must be steady will be steady may change from low to high will change from low to high may change from high to low will change from high to low don?t care: changes allowed changing: state not known n/a center line is high impedance 5v 1533 : 100pf sda output r h c h 10pf c w r l c l r w r total 25pf 10pf macro model 120 100 80 40 60 20 20 40 60 80 100 120 0 0 bus capacitance (pf) min. resistance max. resistance r max = c bus t r r min = i ol min v cc max =1.8k : resistance (k : ) 11 fn8163.2 august 30, 2006 a.c. conditions of test symbol table equivalent a.c. test circuit circuit #3 spice macro model guidelines for calculating typical values of bus pull-up resistors input pulse levels v cc x 0.1 to v cc x 0.9 input rise and fall times 10ns input and output timing levels v cc x 0.5 X9221A
t high t su:sta t hd:sta t hd:dat t su:dat t low t f t su:sto t r t buf scl sda (data in) t aa t dh scl sda sda out (ack) sda out sda out 12 fn8163.2 august 30, 2006 timing diagrams figure 10. input bus timing figure 11. output bus timing a.c. characteristics (over recommended operating cond itions unless otherwise stated) symbol parameter limits unit reference figure min. max. f scl scl clock frequency 0 100 khz 10 t low clock low period 4700 ns 10 t high clock high period 4000 ns 10 t r scl and sda rise time 1000 ns 10 t f scl and sda fall time 300 ns 10 t i noise suppression time constant (glitch filter) 100 ns 10 t su:sta start condition setup time (for a repeated start condition) 4700 ns 10 & 12 t hd:sta start condition hold time 4000 ns 10 & 12 t su:dat data in setup time 250 ns 10 t hd:dat data in hold time 0 ns 10 t aa scl low to sda data out valid 300 3500 ns 11 t dh data out hold time 300 ns 11 t su:sto stop condition setup time 4700 ns 10 & 12 t buf bus free time prior to new transmission 4700 ns 10 t wr write cycle time (nonvolatile write operation) 10 ms 13 t stpwv wiper response time from stop generation 1000 s 13 t clwv wiper response from scl low 500 s 6 X9221A
t su:sto scl sda (data in) t hd:sta t su:sta stop condition start condition scl sda wiper output clock 8 sda in clock 9 ack stop t wr t stpwv start 13 fn8163.2 august 30, 2006 figure 12. start stop timing figure 13. write cycle a nd wiper response timing X9221A
14 fn8163.2 august 30, 2006 X9221A small outline package family (so) gauge plane a2 a1 l l1 detail x 4 4 seating plane e h b c 0.010 b m ca 0.004 c 0.010 b m ca b d (n/2) 1 e1 e n n (n/2)+1 a pin #1 i.d. mark h x 45 a see detail ?x? c 0.010 mdp0027 small outline package family (so) symbol so-8 so-14 so16 (0.150?) so16 (0.300?) (sol-16) so20 (sol-20) so24 (sol-24) so28 (sol-28) tolerance notes a 0.068 0.068 0.068 0.104 0.104 0.104 0.104 max - a1 0.006 0.006 0.006 0.007 0.007 0.007 0.007 0.003 - a2 0.057 0.057 0.057 0.092 0.092 0.092 0.092 0.002 - b 0.017 0.017 0.017 0.017 0.017 0.017 0.017 0.003 - c 0.009 0.009 0.009 0.011 0.011 0.011 0.011 0.001 - d 0.193 0.341 0.390 0.406 0.504 0.606 0.704 0.004 1, 3 e 0.236 0.236 0.236 0.406 0.406 0.406 0.406 0.008 - e1 0.154 0.154 0.154 0.295 0.295 0.295 0.295 0.004 2, 3 e 0.050 0.050 0.050 0.050 0.050 0.050 0.050 basic - l 0.025 0.025 0.025 0.030 0.030 0.030 0.030 0.009 - l1 0.041 0.041 0.041 0.056 0.056 0.056 0.056 basic - h 0.013 0.013 0.013 0.020 0.020 0.020 0.020 reference - n 8 14 16 16 20 24 28 reference - rev. l 2/01 notes: 1. plastic or metal protrusions of 0.006? maximum per side are not included. 2. plastic interlead protrusions of 0.010? maximum per side are not included. 3. dimensions ?d? and ?e1? are measured at datum plane ?h?. 4. dimensioning and tolerancing per asme y14.5m - 1994
15 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn8163.2 august 30, 2006 X9221A plastic dual-in-line packages (pdip) mdp0031 plastic dual-in-line package symbol pdip8 pdip14 pdip16 pdip18 pdip20 tolerance notes a 0.210 0.210 0.210 0.210 0.210 max a1 0.015 0.015 0.015 0.015 0.015 min a2 0.130 0.130 0.130 0.130 0.130 0.005 b 0.018 0.018 0.018 0.018 0.018 0.002 b2 0.060 0.060 0.060 0.060 0.060 +0.010/-0.015 c 0.010 0.010 0.010 0.010 0.010 +0.004/-0.002 d 0.375 0.750 0.750 0.890 1.020 0.010 1 e 0.310 0.310 0.310 0.310 0.310 +0.015/-0.010 e1 0.250 0.250 0.250 0.250 0.250 0.005 2 e 0.100 0.100 0.100 0.100 0.100 basic ea 0.300 0.300 0.300 0.300 0.300 basic eb 0.345 0.345 0.345 0.345 0.345 0.025 l 0.125 0.125 0.125 0.125 0.125 0.010 n 8 14 16 18 20 reference rev. b 2/99 notes: 1. plastic or metal protrusions of 0.010? maximum per side are not included. 2. plastic interlead protrusions of 0.010? maximum per side are not included. 3. dimensions e and ea are measured with the l eads constrained perpendicular to the seating plane. 4. dimension eb is measured wi th the lead tips unconstrained. 5. 8 and 16 lead packages have half end-leads as shown. d l a e b a1 note 5 a2 seating plane l n pin #1 index e1 12 n/2 b2 e eb ea c

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